Character generating apparatus for television titling

ABSTRACT

An apparatus which receives a sequence of character representative signals and which generates stroke signals that are suitable for controlling a scanned display to present the sequence of characters on the display with proportional spacing. The system includes a timing generator for generating timing signals which are synchronized with the display scan and a recirculating storage for storing the character-representative signals, reading out specified character-representative signals which correspond to a specified character in the sequence and then restoring the specified character signals. The recirculating storage is shifted in response to spacer timing signals generated by a spacer detector which is responsive to the specified character signals and includes means for generating spacer timing signals that are a function of the width of the specified character. A stroke generator which is responsive to the timing signals and the spacer timing signals generates a stroke of the specified character.

United States Patent [.1 1

Baron CHARACTER GENERATING APPARATUS FORTELEVISION TITLING [75]Inventor: Stanley N. Baron, Stamford; Conn.

[73] Assignee: Columbia Broadcasting System, Inc,

New York, N.Y.,

[22] Filed: Mar. 29, 1971 [211 App]. No.1 128,727

52 us c1. 340/324 A, 178/30 511 Int. Cl. (106i 3/14 {58] Field of Search340/324 A; 178/30,

[56] References Cited UNITED-STATES/PATENTS 3,165,045 l/l965 Troll.340/324A 3,593,310 7/197] Kievit 340/324 A Primary ExaminerJohn1W..Caldwell. Assistant Exqminerf-Marshall M. Curtis: Att0rny-Spencer E.Olson H SPECIFIED gym 74 753 W/D TH DECODER CHA/MCTER TIM/N6 GENERATORThu/N6 STROKE MEMORY CURSOR VIDEO GENE/M TOR June 19, 1973 571 ABSTRACTAn apparatus which receives a sequence of character representativesignals and which generates stroke signals that are suitable forcontrolling a scanned display to present the sequence of characters onthe display with proportional spacing. The system includes a timinggenerator for generating timing signals which are synchronized with thedisplay scan and a recirculating storage for storing thecharacter-representative signals,

reading out specified character-representative signals which correspondto a specified character in the sequence and then restoring thespecified character signals. The recirculating storage is shifted inresponse to spacer timing signals generated by a spacer detector whichis responsive to the specified character signals and includes means forgenerating spacer timing signals that are a function of the. width ofthev specified character. A stroke generator which is responsive tothe-timing signals and the spacer timing signals generates a stroke ofthe specified character.

15 Claims, 10 Drawing Figures SEQUENCE CONTROLLER SPACER TIM/N6 Puts/5PATENIEQ JUN I 9 '91s 740, 743

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t a o 3 5 5 INVENTOR.

Q Q STANLEY N. BARON Q BY ATTORNEY PATENTED 9 1 sum 07W 10 INVENTOR.

STANLEY N. BARON mw sl QESRN mmbwlm 9w hm 9m hv 9v hm QM MN 9w .3

ATTORNEY PAIENIEIIIIIIII 3.740.143

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INVENTOR.

STANLEY N. BARON a I (041W ATTORNEY PATENTED 9'973 Slit! mar 10 I I|l|Il l I|l| INVENTOR. STA/VLF Y N. BARON A TTORNEY This inventionrelates to a television tilting apparatus and, more particularly, to anapparatus that receives 4 digital input signals corresponding to titleinformation and generates video signals for displaying the informationin readable form.

There have been previously described various systems which convertdigital title information into. video signals that are suitable fordisplay in readable form.-

Systems of this type are employed, for example, to-provide titleinformation alone on a display screen, such as is typically done withfinancial data. Tile information may also be generated for display inconjunction with conventional television picture information. This isgenerally accomplished by combining the video picture signal and thevideo title signal using known keying techniques.

A system that receives digitally coded characters and generatescharacter video signals suitable for display using a televisionrasterscanning pattern is disclosed in the U.S. Pat. No. 3,422,420 ofRJ. Clark. In the Clark system the received digitally coded inputcharacter signals to be displayed in a row are stored in orderedpositions in recirculating shift registers. Various timing signals,synchronized with the display scan, are generated in repetitivesequences and effectively divide the display scan into a plurality ofcharacter space areas" of predetermined equal size. A character patternor outline trace is formed in a character space area on the displaydevice by blanking and unblanking the scanning beam as the beamtraverses the display device. Thus, each character is formed on thedisplay as a series of slices or strokes during successive scanlines.The character signals are read out of the recirculating shift registersone at a time, and a character generator" subsystem generates theappropriate video stroke signals (blanking and unblanking commands)which are distinctive of the character being read out. The timingsignals control the shifting and reading out of the character signals inthe recirculating registers such that a new character signal is read outeach time the display scan passes into a new character space area. Afterbeing read out, each character signals is restored in the recirculatingregisters to be recalled during the next display scnaline when the nextstrokes of each character in the display row are generated. Theretentivity of vision of the eye is relied upon to build up theimpression of a complete character from the separate character strokesthat are produced during each scanline.

Prior art systems such as that disclosed in the Clark patent allotcharacter space areas of a given predetermined width to each characterbeing displayed. In such systems the timing signals are convenientlysynchronized with the display scan and also with the shifting of therecirculating shift registers, so that each character stroke in ascanline is assigned an equal predetermined width. This means, forexample, that the character 1' is afforded the same display width as thecharacter w. Of necessity, the w takes up most of the avilable' widthwhereas the i takes up only a small part of the width of a characterspace area. As a result, the displayed titles appear peculiar to thereader's eye and are somewhat difficult to read due to disproportionatespacing between characters. It is the primary object of the presentinvention to provide a television titling system which generatesproportionally spaced characters for display. 7

SUMMARY OF THE INVENTION The present invention is directed to anapparatus which receives a sequence of character-representative signalsand which generates stroke signals that are suitable for controlling ascanned display to present the sequence of characters on the displaywith proportional spacing. The system includes a timing generator for.generating timing signals which are synchronized with generator whichis responsive to the timing signals and the spacer timing signalsgenerates a stroke of the specified character.

DESCRIPTION OF THE DRAWINGS Other objects, features and advantages ofthe invention will become apparent, and its construction and operationbetter understood, from the following detailed description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is an illustration of the type of character patterns that can beformed using the present system;

FIG. 2 is a schematic block diagram showing the principal components ofthe system;

FIG. 3A and 3B togher is a schematic diagram showing the system ingreater detail;

FIG. 4 is a schematic diagram showing the line and row calculator ofFIG. 3 in greater detail;

FIG. 5 is a schematic diagram showing the spacer detector means of FIG.3 in greater detail;

FIG. 6 is another illustration of the type of character patterns thatcan be formed with the present system along with certain timing diagramswhich relate to the particular characters shown;

FIG. 7 is a schematic diagram showing the character position calculatorof FIG. 3 in greater detail;

FIG. 8 is a schematic diagram illustrating the stream selector circuitryof the system of FIG. 3; and

FIG. 9 is a block diagram illustrating the stroke generator circuitry ofFIG. 3 in greater detail.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Character Display FIG. 1illustrates the type of character patterns which can be formed with thevideo stroke signals generated by the present apparatus. The charactersare depicted trated upper case characters are twenty-eight scanlineshigh, the individual scanlines being denoted as h to'hgg.

Each scanline has a duration of about 64 microseconds. A basic systemclock produces a plurality of pulses during each scanline andeffectively divides each scanline into a plurality of elemental spaces,shown as the horizontal divisions or elements in FIG. 1. Each elementcorresponds to a time duration of about 100 nanoseconds, and the firstcharacter W was arbitrarily chosen as starting at a time t or 100elements (i.e.

10 microseconds) after the beginning of the horizontal scanlinereference.

The row of characters shown in FIG. 1 occupies the portion of the screenfrom t to about 1 so it takes the scanning beam about 9 microseconds totraverse the portion shown during each scanline. During the firstscanline, labeled h,, the top stroke of the character W is displayed byturning the scanning beam on for the periods t r 1 tug, and r Aftera"space of four elements, the beam is again turned on for the period r rto produce the top stroke of the BI, -E," etc. The next horizontalscanline of an interlaced raster scan is ha, which happens to requirethe same strokes as h, for thecharacters shown. For the scanline h,,,the beam is turned on for the periods r I t 2, 5 t, for the E; and soon. In this manner, and with the help of the retenti'vity of vision ofthe eye, the separate character strokes produced during. each scanlinegive the impression of complete characters on the display screen.

It is seen that the characters have differing widths andthat eachcharacter does not occupy an equal-sized character space on the 'displayscreen. For example, among the characters shown, the number of elementalwidths occupied by each character are as follows: W-3l; I-4; -16; andL-16. The characters in a word are proportionally spaced four elementsapart, so that words can be comfortably read and are esthetic'allypleasing.

GENERAL OPERATION The basic operation of the apparatus will nowbedescribed with the aid of FIGS. 2 and 3. In FIG. 2 an input sequence ofcharacter-representative digital signals is received by a recirculatingstorage means 100. These signals are typically in binary form with, forexample, a given six-bit coded input signal representing one of 64 (2)letters, numbers and symbols. The input characterrepresentative signalsmay be derived, for example, from a computer or, as will be furtherdescribed below, from an input keyboard. For the immediate explanationit will be assumed that a sequence of twenty char-' acters is receivedand processed for video presentation in a single row.

The storage means 100 includes a six-level shift register havingaplurality of stages, the number being determined by the'maximum numberof characters to be displayed in a row on the display device. Thereceived signals 10 are stored in sequence in twenty stages of the shiftregister. Upon the appropriate commands, the six bits representative ofthe character in the last stage of the shift register are read out andthen restored to the first stage of the register to be recirculated. Thecharacterread out will bereferred to as the specified characand thenfrom r 1, for the top stroke of the I ter" and its representative bitsor signals as the specified character signals."

A timing generator means 200 receives synchronizing signals from thedisplay device; namely the vertical and horizontal sync signals. Thetiming generator means 200 includes a ten megacycle keyed oscillatorwhich produces basic clock pulses every 100 nanoseconds. The oscillatoris keyed by the horizontal sync signals from the display device. Thetiming genrator also includes various counters which keep track of thenumber of lines scanned by the display up to a given time. When thedisplay scan is in a row area (only a single row of displayed charactersis considered at this point for ease of explanation) the countersproduce signals which indicate which line of the row is being scanned.

propriate stroke of the specified character. The stroke 7 generatormeans includes a read-only memory which is addressed by the receivedcharacter information and by line information. For example, if thereceived information indicates that the specified character is a W andthat the, present display scan-line is h, (FIG. 1), then the memoryoutput stroke bits will be sequential signals instructingthe scanningbeam to turn on" for the intervals r 2 ,5 t 2m and t t The specifiedcharacter signals are also received by a spacer detector 300 whichdetermines the width of the specified character and generates a spacertiming signal which depends upon the time when the horizontally scanningbeam passes out of the display area needed to produce the specifiedcharacter. The spacer timing signals are used to shift the recirculatingstorage means so that the next-character in the sequence becomes the newspecified character in the last stage of the shift register. Theappropriate stroke of the new specified character is then generated. Thespacer detector also generates a coordinating timing signal,synchronized with the spacer timing signal, for controlling the timingassociated with the generation and readout of strike bits.

The operation of the apparatus of FIG. 2 will be better understood byvisualizing the letters of FIG. 1 as being the beginning of the sequenceof the twenty characters to be displayed in a single row. The sequenceof binary coded character-representativesignals are read into therecirculating storage 100 and are stored in order with the W, the I, theE, etc., in adjacent stages of the shift register. The sync signals fromthe display are fed to the timing generator 200, and counters in thetiming generator countthe number of horizontal scanlines of a displayfield scansion until, after a predetermined'number of lines, the displayrow area is reached. The scanlines within the display row are thenseparately counted by the timing generator 200, the first scan-linebeing h, (FIG. 1).

The scanline h, begins its left-to-right scan at a time reference, twhich represents the time at which the horizontal sync signal keys theten megacycle basic clock oscillator. A predetermined time after t thesignals representative of the character in the last stage of the shiftregister (i.e., the specified character W") are fed to the strokegenerator 300 and to the spacer detector-400. The stroke generatorgenerates stroke bits which instruct the scanning beam to turn on forthe appropriate time intervals (t o r 4, 2 tug and t i for character W,-line h;). The spacer detector 400 decodes the character-representativesignals and determines the width of the specified character. In the caseof the W, the character is thirty-one elemental divisions wide, or, inother words, it requires a thirtyone clock pulse duration for display.The spacer detector accordingly generates a spacer timing signal at atime reference 1 that is, thirty-one clock pulses after the initiation(at t of display of the specified character.

The spacer timing signal is fed to the recirculating storage 100 andused to shift the positions of the character-representative signals inthe shiftregister. The W"-is shifted back to the first stage of theshift register and the I moves into the last stage to become the newspecified character. Similarly each character moves up one position sothat the E is in the next-tolast stage, the L in the second-from-laststage, and so on. A coordinating timing signal, which occurs about 400nanoseconds (four elemental divisions) after the spacer timing signal,is also generated by the spacer detector. The coordinating timing signalis fed to the stroke generator.

During the time after occurrence of the spacer timing signal, thescanning beam moves along the space area beginning with the elementaldivision (FIG. 1). Also during this time the binary signalsrepresentative of the character I are fed from the last stage of theshift register to the stroke generator 300 and to the spacer detector400. The stroke generator 300 generates stroke bits which instruct thescanning beam to turn on for a period of four elemental divisions. Thecoordinating timing signal (from the spacer detector 400) controls thestart of the readout of stroke bits to occur at r so that the scanningbeam turns on for thetime interval 1, t Meanwhile, the spacer detectordecodes the new characterrepresentative signals and determines that thespecified character (I) is four elemental divisions wide. The spacerdetector accordingly generates the next spacer timing signal at the timereference r that is, four clock pulses after the initiation (at ofdisplay of the specified character Gili,

In a similar manner the remaining top slices of each of the 20characters are produced during the scanline h,. For the completescanline, the spacer timing signals circulate thecharacter-representative signals in the shift register by exactly onefull cycle, so that at the end of scanline h, the W is again in the laststage of the shift register, the 1" in the next-to-last stage, etc. The-DETAILED OPERATION FIG. 3 illustrates in further detail a preferredembodiment of the apparatus shown in the block diagram of FIG. 2. Therecirculating storage 100, timing generator 200, stroke generator 300,and spacer detector 400 are each shown in dashed blocks with thecomponents contained within each block labeled with a reference numeralin the appropriate hundred series.

In the following description of FIG. 3, it will be assumed that theinput character-representative binary signals 50 are generated from akeyboard (not shown) and that the output stroke bits are displayed on aconventional television monitor (not shown). It will become clear,however, that the stroke bits 80 can most usefully be combined withprogram video and transmitted to remote television receivers.Synchronizing signals 60 from the display monitor are supplied to thetiming generator 200. Also supplied to the timing generator are cursorcontrol signals 70 from the keyboard. The cursor control signalsregulate the relative position on the display at which a given new inputcharacter is to be entered. Cursor video bits control the display on themonitor screen of a cursor dot which gives a continuous visualindication of the status of the cursor control signals. I

The input character-representative signals 50 are stored in a memoryinput buffer and are read into the recirculating shift registers 150 inresponse to signals from the memory input controller and the streamselectors 130. The embodiment of FIG. 3 includes a capability for thedisplay of twelve rows of charactersand there are accordingly twelvegroups of shift registers 150. Each shift register has six parallellevels of fifty stages. so that each display row is potentially capableof displaying 50 characters. (As will later become clear, the actualnumber-of characters which can be displayed on a given row is variablesince it depends upon the widths of the individual character's beingdisplayed.) The shift registers 150 are dynamic MOS registers driven bythe clock drivers and having their stages coupled back to their firststages through the stream selectors 130. The information in each shiftregister is directly recirculated by the stream selectors during most ofthe operating time; i.e., except when new character signals are beingloaded into the shift registers. A more detailed description of theloading process will be deferred until later in the specification. Itsuffices for the present to assume that signals representative of thecharacters to be displayed have been loaded into the shift registers inappropriate sequence and that the stream selectors directly couple thelast and first stages of the registers for a recirculation condition.

The synchronizing signals 60 include the vertical and horizontal syncsignals from the display monitor. The horizontal sync pulses occur onceevery 63.56 microseconds and are used to key the oscillator 210 whichproduces basic clock pulses at a frequency of ten megacycles. Thevisible horizontal scanline duration is about 50 microseconds, so thereare about 500 clock pulses per visible scanline and about 135 clockpulses during each horizontal blanking period.

The display sync signals 60 are received by the line and row calculator230 which counts the horizontal scanlines of the display and keeps trackof the preselected row in which the scanning beam is positioned at anygiven instant. This row information is fed to the memory input control120 and tothe memory output multiplexer so that information will be readinto and out of the appropriate row in the recirculating storage 100.The calculator 230 also keeps track of the line within a row at whichthe beam is positioned '(viz, the h count in FIG. 1); this informationis required by the stroke generator.

The line and row calculator 230, illustrated in further detail in FIG.4, inlcudes counters 231, 232, and 233, each of which may comprise abinary counter. The function of the delayed line counter 231 is toprovide a safe area at the top of the display scan before the start ofthe first row. At the beginning of a new display field scansion, thevertical sync signal resets the counters 232 and 233. The counter 231counts 40 horizontal sync pulses (corresponding to the first 40horizontal scanlines) and produces a signal which enables the automaticline counter 232. The counter 232 counts the next 1? horizontal syncpulses corresponding to the 14 odd (or even) scanlines of the firstcharacter row plus three odd (or even) scanlines constituting a rowspace between the characters in consecutive rows. Each complete row isthus seen to consist of a total of 34 odd and even scanlines. The linecounter 232 produces an output count signal 2320 which indicates theinstantaneous line count within a row; this signal is sent to the strokegenerator 300. Afterreaching a count of seventeen, the automatic linecounter generates a signal which resets inself so that it can startcounting lines within the next row. This signal, 232b, also steps thecount of the automatic row counter 233. The row counter 233 produces anoutput count signal 233a indicative of the instantaneous row count whichis sent to the memory output multiplexer 160 in the recirculatingstorage 100. After reaching a count of twelve, the row counter 233generates a signal 233b which inhibits further row counting until thenext vertical sync pulse resets and enables the row counter 233.

Referring again to FIG. 3, the specified character contained in thememory output buffer 160 is received by a character width decoder 310 inthe spacer detector 300. The character width decoder 310 comprises a.read-only memory, for example, a TTL-type matrix, having eight possibleoutput indications. The decoder 310 receives the specified six-bitsignal representative of one of the 64 possible characters and producesa logical 1 output on one of eight output lines 310a (shown as a singlecable in FIG. 3). Each of the output lines, designated line 0 throughline 7, indicates one' of eight predetermined characters widths. Thecharacters range in width from the four elemental divisions'of the I tothe thirty-one elemental divisions of the W." Actually, there are sevenreal width indications for visible characters with one width signal, forexample the one on line 0, being reserved for the casewhen the specifiedcharacter is a null." A null character-representative signal, (which mayconveniently be 000000") means that the position being read out of therecirculating shift register 50 is empty. A null should not be confusedwith a between-word space, which is another six-bitcharacterrepresentative signal (for example, 0000O1") that presents anacutal space of 16 elemental divisions on the display. As will becomeclear below, there are necessarily some nulls in each row. The widths ofsome representative characters and their corresponding line numbers areindicated in Table I:

TABLE I Width (elemental divisions) null 0 line 0 l, 4 line 1E'.,l'-.,spacel6 line 2 B,l-l, [9 line 3 CR 21 line 4 AN 23 line 5 M 25line 6 W 31 line 7 The coded width signals 31021 are fed to a spacertiming multiplexer 330, which also receives character timing generator320. The timing pulses 320a consist of a series of eight timed pulseswhich occur at intervals that are a function of the elapsed timerequired to scan each of the eight possible character widths. Themultiplexer 330 allows the proper timing pulse, as determined by thecoded width signal 310a, to pass to a sequence controller 340. Thesequence controller 340 generates signals which shift the recirculatingshift registers 50, coordinate the readout of stroke bits from thestroke generator 400, and reset the character timing generator 320.

The operation of the spacer detector 300 can be more clearly understoodby referring to FIG. 5. The character timing generator 320 is shown indashed lines and is seen to include a one-level shift register 321having thirty-two stages. The shift register 321 is clocked by the basicclock pulses from the ten megahertz keyed oscillator 210 (FIG. 3). Theshift register 321 is reset at a time reference T, to a state as shownin FIG. 5 with a l in the first stage and 0s in all other stages. Eachclock pulse advances the 1 to the nextstage of the shift register sothat it takes 32 clock pulses for the l to enter and move through theentire shift register. As an example, after four clock pulses (400nanoseconds after T,,)-' the l is in the stage of the register denoted Rand after 25 clock pulses (2.5 microseconds after T,,) the l is in thestage of the register denoted R Output leads are coupled to eightselected stages of the shift register, namely: R R R R R R R and RPulsesappear on these leads as a result of the l passing through theirassociated shift register stages, and these pulses, T,,, are designatedby their times of occurrence; i.e., T through T The spacer timingmultiplexer includes eight AND gates 331 through 338, each of whichreceives one of the width signal lines 310a and one of the charactertiming pulses 320a. The output of each AND gate is fed to the input ofan OR gate 339, the output of which is a spacer timing pulse occurringat a time corresponding to the end of the stroke of the specifiedcharacter.

The spacer timing pulse is fed to the timing controller 340 whichcomprises a one. level, four stage shift register 341 that operates in amanner similar to the shift register 321. The shift register 341 isclocked by the basic clock pulses from the 10 megahertz keyedoscillator. The spacer timing pulse resets the register 341 to the stateshown in FIG. 5 with a 1" in the first stage (R,,) and 0 in the otherstages (R, to R The next four clock pulses each advance 1 to the nextstage of the register. Outputs 340a, 340b and 3400 appear sequentially,in the manner previously described, after stages denoted R,,.,,, R,,.,,,and R These outputs occur at the times T T and T i.e., one, two, andfour clock pulses, respectively, after T,,, where T, is the time ofoccurrence of the spacer timing pulse relative to the time referenceT,,. The output 340a is used to clock the recirculation shift registers50, and the output 340b is fed to a horizontal position counter 220which will be described hereinbelow.

The last output 34C is sent to the stroke memory and triggers thereadout of stroke bits from the stroke memory. The output 340ccontemporaneously resets the shift register 321 in the character timinggenerator 320. It should be noted that at the beginning of each scanlinea signal is needed to initially set register 321. For this purpose, thesignal designated horizontal synch reset which is synchronized withhorizontal flyback, is applied to the register, the signal being timedto occur a few microseconds afterthe beginning of each horizontal lineand determines the relative positions of the first character of eachrow.

As an illustration of the operation of the spacer detector means 300,and referring to FIGS. 3, and 6, assume that the specified characterjust read into both the character width decoder 310 and stroke memory isan F, and that the next characters to be read in are an R an I and a W(FIG. 6). An F is sixteen elemental divisions wideand will produce alogical 1" on line 2 of the lines 340a (Table I). Line 2 is one of thetwo inputs to the AND gate 333. The shift register 321 is reset at thetime reference disignated T which corresponds to the time atwhich thestroke memory is'triggered to begin reading out the stroke bits of the Ffor display. (Both of these events are precipitated by the signal 340cwhich occured at the time reference T of whatever character was readoutb efore the F.) The next clock pulse moves the 1 in shift register321 into the second stage and also causesthe readout of the first strokebit of the F from the stroke generator. As demonstrated above, thepulses T T 3, T1 etc. occur four, sixteen, nineteen, etc. clock pulsesand after T,,. 0nly the pulse T is'passed through its AND gate 333,however, since the other AND gates do not have 1s on their line 310ainputs. As a result, the spacer timing pulse T appears at the output oftheOR gate 339 16 clock pulses after the beginning of the readoutof theF stroke bits. Also, since'the F" is sixteen elemental pulse later (atT,,,,), or, 17 clock pulses after T,,, the

signal 340a-shifts the-recirculating registers and the next character,R," becomes the new specified character read into the character widthdecoder and the stroke memory. Four clock'pulses after T (i.e., atT,,,..,) the signal 340c'enablesthe stroke memory'to begin reading outthe stroke bits of the new specified character, R4 The signal 340C alsoresets the shift register 321 and establishes a new time reference T forthe An R-' is 2] elementaldivisions wide and will produce a logical l online 4 of thelines-3l 0a (Table I), causing the pulse T passing throughthe AND gate 335 to become the spacer timing pulse. The R, being 21elemental divisions wide, requires a 21' clock pulse duration for thereadout of its stroke bits. Thus, as before, the spacer timing pulseoccurs simultaneously with the readout of the last stroke bit of thecharacter being read out of the stroke memory. The same is true for theI" and the W which follow.

The timing of the pulses at 340C, the'spacer timing pulses, andthepulses of340a '(FIG. 4) are shown in FIG. 6 in timed relationship tothe readout of characters. (The scale directly below the charactersindicates the number of elapsed clock pulses from the time reference Tof the first character shown, viz.,-F.") As seen from the timingdiagrams, the timing reference, T for each character occurs one clockpulse before the first stroke bit of the character is read out. Thespacer timing pulses occur during the last stroke bit of the characterbeing read out. Also, the pulses 340a, which serve to shift therecirculating registers (FIG. 3), occur during the next clock pulseafter the spacer timing pulse.

It should be noted that for each stroke of a given character (i.e.,during successive scanlines), the timing of the spacer timing pulse andthe timing of the outputs of the sequence controller 340 are the same.In other words, the particular stroke pattern of a character, which mayvary from scanline to scanline, does not affect the relative timing ofthe spacer timing pulse and its related sequence controller outputs. InFIG. 6, for

example, the first scanline of the F requires stroke bits which unblankthe display beam for the entire sixteen element width of the character.For, the last scanline of the F, only the first-four stroke bits shouldunblank the display beam while thelast twelve stroke bits should blankthe display beam. In either case, however, the stroke pattern for the F"is considered to have a sixteen clock pulse duration and the timing ofthe spacer timing pulse and its related sequencecontroller outputs areas shown in FIG. 5.

Theloading of new characters into the recirculating shift registers 150'can now be conveniently described infdetail. Referring again to FIG. 3,the cursor control signals 70 are received by a character positioncalculator 220. As was previously indicated, the cursor control signalsoriginate from a keyboard and regulate the relative position on thedisplay at which a given new input character is to be entered. Thecursor video signals 90 (the generation of which is to be hereinafterdescribed) control the display on the monitor screen of a cursor dotwhich gives an operator a continuous visual indication of the status ofthe cursor control signals.

Referring to FIG. 7, the character position calculator 220 includescounters 221, 222 and 223 and a comparator 224. The cursor controlsignals include a row advance pulse signal 71, and a position advancepulse"v signal 72 which are generated whenthe operator depresses a keyon the keyboard which affects the cursor. Themanual row counter22l is abinary counter whose output count (a number from one to twelve)indicates the display row in which the next new character is to beentered. In other words, the row counter 221 indicates which row of theshift registers (FIG. 3) is to receive the next new character. The

. manual horizontal position counter 222 is also a binary counter whoseoutput count (a number from one to fifty) indicates the horizontaldisplay position at which the the next new character is to be entered.In other words, the count'er222 indicates the particular stage of theshift register 150 in which the next new character can be entered. Thus,for example, if the next character to be entered is to go into the tenthstage of the. third row of shift registers, the counter 221 wouldindicate a count of three and the counter 222 would indicate a count often". Each ofthe counters shifts back to a count of one when pulsed fromits highest possible count.

The operator manipulates the status of the cursor by using the keyboardto generate the signals 71, 72, The cursor status may be changed by theoperator without entering new characters to the display by depressingkeys on the keyborad (not shown) designated as cursor position advanceor cursor row advance." Depressing the,cursor position advance keygenerates a pulse 72 which steps the counter 222 by one and also movesthe displayed cursor dot by one horizontal position as will be shown.Depressing the cursor row advance key generates a pulse 71 which stepsthe counter 221 by one and accordingly moves the displayed cursor dot tothe next row.

The cursor status i's also changed automatically when a character isentered on the display by depressing a character key. When a characterkey is depressed the six-bit input character-representative signals 50are generated by the keyboard logic an entered into the memory inputbuffer 110 (FIG. 3). Also, a position advance pulse 72 and a preliminaryenable signal 73 (FIG. 7) are generated.-The pulse 72 thus steps thecounter 222 by one when a new character is entered. Generally, theoperator will be entering a sequence of characters to form a word bysuccessively depressing the appropriate character keys. As an example,referring again to FIGS. 3, 6 and 7, assume that the F, R'and I (FIG.6)'have been entered as the first three characters of thefirst row ofdisplay and occupy thefrrst three positions of the row 1 shift registor150 (FIG. 3) In this condition the manual horizontal position counter222 will contain a count of"four," having been stepped, by one one) foreach of the'three entered characters. Also, the displayed cursor'dot'would be in the position shown by the dot 601 ofFlG. 6 and wouldindicate to the operator that the next character to be entered will gointo a positionto the right of the I on the display. Now, if theoperator depresses the W key, the W character signals will enter thefourth position of the row 1 shift register 150 (in a manner to beshown) and the;

W .willappear on the display. The pulse 72, generated when the W keyvwas depressed, will step the counter 222 to a count offive and thedisplayed cursor dot will appear to jump to the position indicated bythe dot 60.2. The actualgeneration of the cursor video will be treatedin more detail in a later portion of the specification. It suffices forthe present to appreciate that the cursor position is defined by thestates of the counters 221 and 222. I

The automatic horizontal position counter 223 is a binary counter which,like the manual horizontal position counter 222, produces output countsfrom -one" to fifty."-2'Ihe counter 223 is reset to one" at thebeginning of each display scanline (by the horizontal sync signal) andcounts to fifty" during each scanline. The counter 223 is stepped by'thepulses 34011 (FIGS. 3 and 5); which, it will be recalled, occur duringthe next clock pulse each time the recirculating registers are shiftedby the pulse'340a. Thus, the pulses 340b are counted by the automatichorizontal position counter 223 to keep track of whichcharacter positionof the shift registers 150 is being read out of the last stage of theshift registers and restored to the first stage. As will be seen, thisinformation is needed so that new characters can be entered in theappropriate position of the selected shift register.

(from an original count of I The outputs of the counters 222 and 223 arecompared by the horizontal position comparator 224 containing logicwhich produces a position enable signal 224a when the count of counter222 is the same as that of the counter 223. The signal 224a, whichoccurs once every scanline, is thus timed to occur exactly when thecontents of the desired stage of the shift register is being read out.

Depressing a particular character key on the keyboard automaticallygenerates a preliminary enable signal 73 which immediately resets theflip-flop-250 designated as the load command generator. As soon as theposition enable signal 224a occurs, the flip-flop of the commandgenerator 250 is set and produces a load command pulse 250a. The loadcommand pulse is received by the memory input controller 120 (FIG. 3)which directs theload command pulse to the stream selector circuitry ofthe row into which the new character is to be entered. The memory inputcontroller 120 also receives the manual row count which is the desiredinformation as to which rowin which the new character is to be entered)in binary form. The input controller 120 includes a conventional logicdecoder which converts the binary row count to an activated signal onone of-twelve lines. The load command pulse 250 is then ANDed with theactive line to produce a Load Row N (where N is the appropriate rownumber from one to twelve) signal 120a.

FIG. 8-illustrates the functioning of the stream selector circuits 130and specifically shows,'as representative, the stream selector circuitryfor the first, second and sixth levels of shift registers of Row 1. Thestream selector circuitry for each levelis seen to include-an inverterI31, AND gates 132 and 133, and an OR gate 134. As was indicated above,the memory input controller 120 produces a Load Row N signal on one ofits twelve outputs at the time at which the new character bits are to beentered in the appropriate stage of the selected shift register 150.During most of the operating time of the equipment, the Load Row Nsignals are off and are therefore at a logical 0" level. This produces arecirculating condition of the shift registers as can be seen, forexample, by assuming that the Load Row 1 signal is at0 in FIG. 8. Underthis condition, the outputsof the AND gates 133 are each 0" (since eachhas a 0 input), and the output of each OR" gate 134 therefore tracks"the-output of the AND gate 132 which feeds it. Each of the AND gates 132receives a 1 input (an inverted 0) from the inverted 131; the output ofeach AND gate 132 is therefore determined by its other input, viz thebit 150a fed back back from the last stage of the shift register. Itfollows that the output 150a of the last stage of the shift register isfed back through the gates 132 and 134 to the firststage of theshiftregister. When the Load Row 1" signal is at a logical 1" level,however, the outputs of the inverters 131 are at 0 and the gates 132also-have 0 outputs. In this case, the AND gates 133 are seen to beactive, each having an output which corresponds to its data bit input.The six data bits are thus passed through the OR gates 134 and intoposition in the shift register'in place of the six old bits which hadpassed out of the last stage of the register.

Referring again to FIG. 3, the outputs 150a of the shift registers areeach received by the memory output multiplexer 160. The shift registers150 are all shifted simultaneously by the clock drivers 140 so that themultiplexer 160 constantly receives twelve groups (one for each row) ofnew six-bit character-representative signals at once. Only thecharacters of the row being displayed are read out of the multiplexer160 (one at a time), however. The multiplexer 160 receives the binarycoded row count from the automatic row counter 233 (FIG. 4) in theautomatic row calculator 230. The multiplexer 160 includes conventionaldecoder logic which converts the binary number (from one to twelve") toan output signal on one of twelve output lines. The appropriate row ofshift register outputs is then selected by multiplexing circuitry of thetype shown in multiplexer 330 (FIG. 5).

FIG. 9 illustrates the functioning of the stroke generator 400 whichincludes the stroke memory 410 and the cursor video generator 420. Thestroke memory 410 includes a read-only memory (ROM) unit 411 whichreceives the specified character signals and the line information 232afrom the automatic line counter 232 (FIG. 4). Read-only memories aredescribed, for example, in an article by F. Kvamme which appeared atpage 88 of the Jan. 5, 1970 issue of Electronics. The ROM 411 generatesthirty-one stroke bits which are entered in parallel into theparallel-in-serial-out shift register 412'. The stroke bits areclocked-out serially using the basic clock pulses from the keyedoscillator 210 (FIG. 3). The readout of stroke bits is indicated by theenabling of the register 412, which is accomplished by the coordinatingtiming signal 340c from the sequence controller 340.

It should be understood that most characters consist of less than 3lstroke bits. For example, the top stroke line of an I consists of thefour stroke bits 1111. The remaining bits (5 through 31) read out of theROM are "s. These Os do not have a chance to be read out, however. Afterthe fourth stroke bit, the signal 340a .(FIG. shifts the recirculatingregisters 150 and a new specified character, is read into the ROM. Theshift register 412 is then reloaded and does not begin its next readoutuntil enabled again by the coordinating timing signal.

The cursor video generator 420 includes a comparator 421, a gate 422, asmall-scale ROM 423, and a four stage parallel-in-serial-out shiftregister 424. The row comparator 421 receives the outputs of the manualrow which the cursor is set. The signal 421a and the position enablesignal 224a (FIG. 7) are received at the input of the gate 422. Theposition enable signal 224a,

it will be remembered, occurs when the manual horizontal positioncounter has a count which is the same as the automatic horizontalposition counter 223 (i.e., at the selected cursor position). When thesignals 421a and 2240 are both present,the gate 422 allows the lineinformation signal 232a to pass to the ROM 423. If the particularscanline is one of the last six scanlines of a character row, the ROM423 generates four stroke bits consisting of either 01 I0 or llll (seedot contiguration of FIG. 6). These bits are entered in parallel intothe four-stage parallel-in-serial-out shift register 424. The readout ofthe bits is then triggered by the coordinating timing signal 340C.

The stroke bits are typically combined with ordinary program video usingconventional keying techniques and the composite video can then betransmitted. The cursor stroke bits are additionally keyed into thevideo 5 which is displayed on the operators control monitor. The cursorvideo generally is not transmitted with the composite program video andcharacter stroke bits.

While the invention has been described with refer ence to a particularembodiment, it will be appreciated that numerous variations can be madewithin the spirit of the invention. For example, the vertical andhorizontal sync signals are shown as derived from a display (e.g., theoperators control monitor). Alternatively, an external source of syncsignals can be used to snychronize the program video, the operator'sdisplay and the titling apparatus.

I claim:

1. Apparatus for receiving asequence of characterrepresentative signalsand for generating video control signals which are suitable forcontrolling a scanned display to present the sequence of characters onthe display, comprising:

timing generator means for generating timing signals which aresynchronized with the display scan; recirculating shift register, meansfor storing the character-representative signals, reading out specifiedcharacter-representative signals which correspond to a specifiedcharacter in thesequence, and

re-storing the specified character-representative signals; 7

spacer detector means responsive to the specifiedcharacter-representative signals and including means for generatingspacer timing signals, the timing of which is a function of the width ofthe specified character, the recirculating shift register means beingshifted in response to the spacer timing signals; and

stroke generator means responsive to said timing signals suitable andsaid specified characterrepresentative signals for generating videocontrol signals for producing a stroke of the specified character on adisplay.

2. Apparatus as defined by claim 1 wherein said stroke generator meansis also responsive to said spacer timing signals which triggers thereadout of said video control signals from said stroke generator means.

3. Apparatus as defined by claim 1 wherein said spacer detector meansincludes:

a character timing pulse generator for generating a plurality of timingpulses each of which is representative of a predetermined timingreference assciated with a predetermined character width;

a character width decoder for receiving said'specified character signalsand for generating a width signal indicative of the width classificationinto which the specified character falls;

a spacer timing multiplexer responsive to said width signal for choosinga selected timing pulse which corresponds to the width of the specifiedcharacters; and

a sequence controller responsive to said selected timing pulse and tosaid timing signals from said timing generator means for generating saidspacer timing signals.

4. Apparatus as defined by claim 3 wherein said character timinggenerator comprises a serial-in-parallelout shift register.

5. Apparatus as defined by claim 4 wherein said sequence controllercomprises a serial-in-parallel-out shift register which is reset by saidselected timing pulse.

6. Apparatus as defined by claim 5 wherein one of said spacer timingsignals 'is applied to and is operative to reset said character timinggenerator.

7. Apparatus as defined by claim 1 wherein said re- I circulatingstorage means comprises a plurality of recirculating shift registers,one for each of a predetermined number of rows of characters to bedisplayed.

8. Apparatus as defined by claim 7 wherein the scanned display exhibitsa television raster scan-line pattern having a plurality ofsubstantially parallel syning automatic position counting meansresponsive to said spacer timing signals for counting the number ofcharacters occurring during a given scanline.

12. Apparatus as defined by claim 11 further comprising manual positioncounting means responsive to external signals indicative of the position,at which a new character is to be entered on the display.

13. Apparatus as defined by claim 12 further comprising load controllingmeans responsive to said manual and automatic counting means andoperative to generate a load command signal at a time at which a newcharacter is to be entered into said recirculating storage means.

14. Apparatus as defined by claim 13 further comprising manual rowcounting means responsive to external signals indicative of the row inwhich said new character is to be entered on the display.

15. Apparatus as defined by claim 14 further comprising cursor videogenerating means responsive to said manual position counter and saidmanual row counter and operative to generate cursor control signalssuitable for controlling said display to present thereon an indicationof the position on the display at which a new character is to beentered.

1. Apparatus for receiving a sequence of characterrepresentative signalsand for generating video control signals which are suitable forcontrolling a scanned display to present the sequence of characters onthe display, comprising: timing generator means for generating timingsignals which are synchronized with the display scan; recirculatingshift register means for storing the characterrepresentative signals,reading out specified characterrepresentative signals which correspondto a specified character in the sequence, and re-storing the specifiedcharacter-representative signals; spacer detector means responsive tothe specified characterrepresentative signals and including means forgenerating spacer timing signals, the timing of which is a function ofthe width of the specified character, the recirculating shift registermeans being shifted in response to the spacer timing signals; and strokegenerator means responsive to said timing signals suitable and saidspecified character-representative signals for generating video controlsignals for producing a stroke of the specified character on a display.2. Apparatus as defined by claim 1 wHerein said stroke generator meansis also responsive to said spacer timing signals which triggers thereadout of said video control signals from said stroke generator means.3. Apparatus as defined by claim 1 wherein said spacer detector meansincludes: a character timing pulse generator for generating a pluralityof timing pulses each of which is representative of a predeterminedtiming reference assciated with a predetermined character width; acharacter width decoder for receiving said specified character signalsand for generating a width signal indicative of the width classificationinto which the specified character falls; a spacer timing multiplexerresponsive to said width signal for choosing a selected timing pulsewhich corresponds to the width of the specified characters; and asequence controller responsive to said selected timing pulse and to saidtiming signals from said timing generator means for generating saidspacer timing signals.
 4. Apparatus as defined by claim 3 wherein saidcharacter timing generator comprises a serial-in-parallel-out shiftregister.
 5. Apparatus as defined by claim 4 wherein said sequencecontroller comprises a serial-in-parallel-out shift register which isreset by said selected timing pulse.
 6. Apparatus as defined by claim 5wherein one of said spacer timing signals is applied to and is operativeto reset said character timing generator.
 7. Apparatus as defined byclaim 1 wherein said recirculating storage means comprises a pluralityof recirculating shift registers, one for each of a predetermined numberof rows of characters to be displayed.
 8. Apparatus as defined by claim7 wherein the scanned display exhibits a television raster scan-linepattern having a plurality of substantially parallel synchronizedscanlines.
 9. Apparatus as defined by claim 8 further comprisingautomatic line counting means responsive to synchronizing signals fromsaid scanned display and operative to count a predetermined number oflines within each display row.
 10. Apparatus as defined by claim 9wherein said timing generator means includes means for generating apredetermined number of clock pulses during each scanline.
 11. Apparatusas defined in claim 10 further comprising automatic position countingmeans responsive to said spacer timing signals for counting the numberof characters occurring during a given scanline.
 12. Apparatus asdefined by claim 11 further comprising manual position counting meansresponsive to external signals indicative of the position at which a newcharacter is to be entered on the display.
 13. Apparatus as defined byclaim 12 further comprising load controlling means responsive to saidmanual and automatic counting means and operative to generate a loadcommand signal at a time at which a new character is to be entered intosaid recirculating storage means.
 14. Apparatus as defined by claim 13further comprising manual row counting means responsive to externalsignals indicative of the row in which said new character is to beentered on the display.
 15. Apparatus as defined by claim 14 furthercomprising cursor video generating means responsive to said manualposition counter and said manual row counter and operative to generatecursor control signals suitable for controlling said display to presentthereon an indication of the position on the display at which a newcharacter is to be entered.